1. Field of the Invention
This invention relates to solid-state image sensing devices and, more particularly, to the construction of a solid-state image sensing device having an overflow drain structure for checking the blooming phenomenon. Further, the invention relates to methods of manufacturing the overflow drain structure of the solid-state image sensing device.
2. Description of the Background Art
The solid-state image sensing device has three basic functions which are photoelectric conversion, charge storage and scanning. It is an image converting device which stores charges proportional to quantities of incident light in respective pixels arranged in a mosaic pattern, and reads out variations in the charges proportional to intensities of incident light by electrically switching these pixels in succession.
Solid-state image sensing devices are classified broadly into two types, i.e. the interline transfer type and frame transfer type. The construction of a conventional solid-state image sensing device of the interline transfer type will be described with reference to FIGS. 10 and 11. FIG. 10 is a plan view of the conventional solid-state image sensing device. FIG. 11 is a section taken on line A--A of FIG. 10. A solid-state image sensing device having the illustrated construction is disclosed in Japanese Patent Laying-Open No. 59-105779, for example.
Referring to these drawings, the interline transfer type solid-state image sensing device comprises a photosensitive, vertical charge transfer section 1, a horizontal charge transfer section 2, and overflow drain sections 3. The photosensitive, vertical transfer section 1 includes photoelectric conversion regions 4 and vertical charge transfer regions 5. The photoelectric conversion regions 4 include a plurality of n-type impurity regions 7 arranged in a matrix form on a main surface of a p-type silicon substrate 6.
The vertical charge transfer regions 5 include channel regions 8, insulating films 9 and transfer electrodes 10. The channel regions 8 comprise n-type impurity regions formed on the main surface of the p-type silicon substrate 6. The transfer electrodes 10 comprise a plurality of polysilicon conductive layers aligned in a direction of charge transfer.
A p+ impurity region 11 is formed between each n-type impurity region 7 of the photoelectric conversion regions 4 and each channel region 8 of the vertical charge transfer regions 5. The transfer electrodes 10 partly overlie the p+ impurity regions 11 with the insulating films 9 in between. The p+ impurity regions 11, extensions of the transfer electrodes 10 and insulating layers 9 constitute read gates 12.
The overflow drain sections 3 are opposed to the vertical charge transfer regions 5 across the photoelectric conversion regions 4. The overflow drain sections 3 include p+ impurity regions 13 and n-type impurity regions 14 formed on the main surface of the p-type silicon substrate 6, and gate electrodes 14 formed on the insulating films 9. Each overflow drain section 3 has a construction of a MOS (metal oxide semiconductor) transistor having the n-type impurity region 7 of the photoelectric conversion region 4 acting as the source, the n-type impurity region 14 acting as the drain, and the p+ impurity region 13 acting as the channel.
Element isolating and insulating oxide films 16 are formed on selected regions of the main surface of the p-type silicon substrate 6. The element isolating and insulating oxide films 16 provide insulation and isolation between the vertical charge transfer regions 5 and overflow drain regions 3 lying adjacent to each other and between the aligned n-type impurity regions 7 of each photoelectric conversion region 4.
The horizontal charge transfer section 2 comprises a charge transfer CCD (charge coupled device).
The overflow drain sections 3 are connected to a purge drain 17. The purge drain 17 is formed in an opposite position to the horizontal charge transfer section 2.
An operation of the solid-state image sensing device will be described next with reference to FIGS. 12A and 12B. FIG. 12A is a schematic plan view of the solid-state image sensing device illustrating the operation thereof. FIG. 12B is a timing chart of the operation of the solid-state image sensing device. Referring to these drawings, the photoelectric conversion regions 4, which comprise a plurality of photodiodes, are connected respectively through the read gates 12 to the vertical charge transfer regions 5 aligned vertically. When light enters the photoelectric conversion regions 4, the photodiodes constituting the photoelectric conversion regions 4 become optically charged. The optical charges accumulate during a vertical blanking period. When gate pulses P2 are applied to the read gates 12, the charges are read to the vertical charge transfer regions 5 all at once. The optical charges thus read are transferred through the vertical charge transfer regions 5 to the horizontal charge transfer section 2. A signal corresponding to one line is taken out as a video signal output during each horizontal scan period. This function is termed electronic shutter function.
On the other hand, during a vertical effective scan period for transferring effective optical charges to the horizontal charge transfer section 2, superfluous charges are generated in the photoelectric conversion regions 4 by light continuously impinging thereon. The overflow drain structure is operable to purge these superfluous charges
outwardly of the device. More particularly, gate pulses P1 of a predetermined voltage are applied to the gate electrodes 15 of the overflow drain sections 3 at predetermined intervals of time during the vertical effective scan period. As a result, the superfluous charges generated in the photoelectric conversion regions 4 are transferred to the purge drain 17 through the n-type impurity regions 14, and are then purged outwardly. In this way, a clear image may be reproduced by the shutter function which reads or purges effective optical charges and superfluous charges at predetermined time intervals.
The above example is a solid-state image sensing device including a flat type overflow drain structure having overflow drain sections 3 arranged parallel to the photoelectric conversion regions 4 on the main surface of the semiconductor substrate. This construction has the disadvantage that the presence of overflow drain sections 3 allows the photoelectric conversion regions to occupy a reduced proportion of the main surface of the semiconductor substrate or increases a required area of the main surface of the substrate. In view of the above situation, a device has been proposed which prevents the overflow drain structure from causing a substantial reduction in the area allocated to the photoelectric conversion regions and the like. This example will be described with reference to FIG. 13. FIG. 13 is a sectional view of a solid-state image sensing device having what is known as a vertical overflow drain structure. Such a structure is disclosed in Japanese Patent Laying-Open No. 63-27057, for example.
Referring to FIG. 13, this solid-state image sensing device comprises overflow drain sections 3, photoelectric conversion regions 4, vertical charge transfer regions 5 and read gates 12.
The illustrated device further comprises p-wells 19 of p-type impurity regions formed on a main surface of an n-type silicon substrate 18. Further, n-type impurity regions 7 are formed on surface regions of the p-wells 19. The regions having these n-type impurity regions 7 constitute the photoelectric conversion regions 4.
The vertical charge transfer regions 5 include channel regions 8 comprising n-type impurity regions formed on surfaces of the p-wells 19, and transfer electrodes 10 formed on an insulating film 9. The transfer electrodes 10 comprise a plurality of electrodes aligned in a direction of optical charge transfer.
The read gates 12 include gate electrodes 15 formed on the insulating film 9. Each gate electrode 15, insulating film 9 and n-type impurity region 7, and channel region 8 constitute a MOS transistor.
Each overflow drain section 3 is defined in a groove 21 formed in the main surface of the n-type silicon substrate 18. An insulating film 22 is formed on inside walls of each groove 21. Further, a gate electrode 23 is formed on a surface of the insulating film 22. This overflow drain section 3 defines a MOS transistor having the gate insulating film 22 and gate electrode 23, with the n-type impurity region 7 acting as a source region, and the n-type silicon substrate 18 acting as a drain region. A channel stop region 24 comprising a high-density p-type impurity region is formed on a side face of the groove 21 closer to the vertical charge transfer region 5.
An operation of the overflow drain sections 3 will be described next. Optical charges are generated in the n-type impurity regions 7 of the photoelectric conversion regions 4 by light impinging thereon. When superfluous charges are generated by intense incident light, a predetermined voltage is applied to the gate electrodes 23. As a result, inversion layers are formed on surfaces of the regions of the p-wells 19 opposed to the gate electrodes 23. The superfluous charges are purged to the n-type silicon substrate 18 through these inversion layers. The channel stop region 24 is formed on one side of the groove 21. Therefore, a channel is not formed on the side having the channel stop region 24 even when the predetermined voltage is applied to the gate electrodes 23. This operation performs the element isolating function.
The solid-state image sensing device having the vertical overflow drain structure is effective to reduce the surface area occupied by the overflow drain sections, compared with the solid-state image sensing device having the conventional flat type overflow drain structure.
As described above, the conventional solid-state image sensing devices have one overflow drain section for one photoelectric conversion region. The device has relied for its microminiaturization on a reduction in size of the overflow drain sections, but nothing has been achieved with respect to the arrangement of elements on the main surface of the semiconductor substrate.